UET researchers design System on Chip

LAHORE:A team of researchers at the Department of Electrical Engineering, University of Engineering and Technology (UET), has designed a ‘System on Chip’ (SoC) integrating a processor core with multiple peripherals for embedded applications.

According to a press release, the designed SoC (UETRV_ESoC) consists of a three-stage pipelined RISC-V processor core, three motor control modules, each capable of controlling dc-servo motors for coordinated multi-axis motion control, along with a few other peripherals. UETRV_ESoC is open-sourced and is available at the UET Department of Electrical Engineering’s GitHub codebank. UETRV_ESoC has also been selected for the fabrication in the Open Source MPW-5 Shuttle programme which is sponsored by Google. The team comprising Umer Shahid, Abdul Wadood, Ali Imran, Junaid Amjad and Prof Dr Muhammad Tahir has successfully accomplished the goal and aspired to make many more such contributions to the open-source community in future. The team is thankful to its alumni and acknowledges their support in equipping Digital System Design Laboratory with necessary resources. UET Vice Chancellor, Dr Syed Mansoor Sarwar, has congratulated all the contributors and stakeholders for the success of this project. He added that this success would motivate further research and development efforts in the domain of digital IC/SoC design in Pakistan.

Dr Sarwar said, “We have already established a laboratory for IC design and testing at the UET through funding from the Punjab government and have a plan for enhancing our expertise and graduate degree programme in this area.” The world is facing a serious shortage of ICs because of their increasing demand due to proliferation of Internet of Things (IoT), he said, adding, “In an era of severe shortage of IC designers, design verification experts, and fabs, we must grab the opportunity to produce graduate in this important area of engineering and technology as well as re-train graduated engineers.”